- From commodity chips to AI accelerators
- Four value pools: design, software, packaging, foundry
- Unit economics for AI silicon
- Policy levers and talent hubs
- Risks and execution checklist
The short
- Design IP first. Fabless RISC-V and domain-specific accelerators offer quicker returns than full fabs.
- Software stack wins adoption. SDKs and compilers are as critical as silicon.
- Packaging matters. HBM and interposer tech shape performance per watt.
Value pools
1) Fabless design
Custom accelerators for inference and edge workloads. Moat IP + ecosystems
2) Software & toolchains
Compilers, runtimes, quantisation frameworks. Lock-in Developer adoption
3) Packaging & test
2.5D/3D packaging, HBM integration, thermal management. Revenue Higher ASP
4) Foundry
Specialty sensors, mature nodes; AI-tuned cutting-edge nodes remain import-dependent.
Unit economics
| Driver | Why | Notes |
|---|---|---|
| Yield | Gross margin | Advanced nodes amplify yield impact |
| HBM cost | Perf/watt | Packaging drives BOM swings |
| Software maturity | Time to market | Shorter POCs mean faster adoption |
Policy & talent
- Fund EDA, compilers, runtimes — not just fabs
- Anchor orders with public-sector AI deployments
- Link universities to startup tape-outs
Risks
- Export controls on advanced GPUs
- HBM supply constraints
- Talent churn